Modern computer systems have a main memory of semiconductor circuits which is large but relatively slow. Due to advances in technology, it is now possible to buy a central processing unit (CPU) which is significantly faster than the typical main memory. Consequently, significant inefficiency would result if the CPU had to stop and idle briefly during each memory access cycle while it waited for the memory. Although faster semiconductor memory components are available, they are significantly more expensive than slower components, and it is thus not cost effective to provide an entire main memory made from the faster memory components.
As a compromise, computer systems frequently include a cache memory which is made from the faster memory components and which is smaller than the main memory. When a data word is read from the main memory, a duplicate is stored in the cache memory, and if the CPU subsequently attempts to read the same data from the main memory, the cache memory will intervene and provide the data to the CPU much faster than the main memory could so that the CPU does not have to stop and wait. Usually, the entire cache memory can be enabled or disabled as a whole by the software.
Certain portions of a main memory can be separate conventional printed circuit cards which are plugged into connectors or slots provided in the computer. However, the same connectors or slots will accept other conventional circuit cards which in some respects appear to the CPU to be memory locations but which do not actually function as true memory locations. If a cache memory attempts to maintain a duplicate of data for such locations, errors will result. Although it is possible for software to attempt to keep track of these nonstandard locations and to turn off the cache memory when these locations are being accessed, the approach is cumbersome, not suitable for all applications, and requires additional processing by the CPU which reduces processing efficiency.
A further consideration is that, when a cache memory is turned off, updates of the data in it cease, and thus when the cache memory is again turned on it does not cause a noticeable system speed increase until a number of memory cycles have been performed and it again contains a useful quantity of up-to-date duplicate information.
It is therefore an object of the present invention to provide a control arrangement for a cache memory which facilitates flexibility in defining the memory addresses for which operation of the cache memory is and is not permitted.
A further object of the invention is to provide such a control arrangement which is relatively inexpensive, and which requires minimal additional hardware or software.
A further object is to provide a control arrangement for a cache memory which can operate the cache memory in a mode in which the transmission of data from the cache memory to the CPU can be inhibited while the cache memory nevertheless continues to be updated.
The objects and purposes of the invention, including those set forth above, are met by providing a method and apparatus involving a main memory having a plurality of sections which each include a plurality of selectively addressable storage locations, a cache memory, and an accessing arrangement for successively requesting data from respective locations in the main memory, each section of the main memory being associated with a changeable status condition which is one of a caching enabled status and a caching disabled status, and reading and storing of data by the cache memory is inhibited when data requested by the accessing unit is in one of the sections of the main memory having the caching disabled status.
The objects and purposes are also met by providing a method and apparatus in which the data in a cache memory can be updated even when reading of data from the cache memory is inhibited.